1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly to a Magnetic Random Access Memory (MRAM) that nonvolatilely stores data, utilizing a magneto-resistance effect. More particularly, the present invention relates to a spin injection type MRAM which is configured to set magnetization directions, or the resistance state of a magnetic storage element by spin injection.
2. Description of the Background Art
The nonvolatile semiconductor memory device can hold storage data even when the power is shut down, and therefore it is not necessary to supply the power during a standby state. Therefore, the nonvolatile semiconductor memory devices have been widely used in portable equipments and others to which low power consumption is required.
An MRAM utilizing a magneto-resistance effect is one of such nonvolatile semiconductor memory devices. In the MRAM, a storage element includes a fixed layer having its magnetization direction set fixedly, and a free layer having its magnetization direction set according to storage data. When the magnetization directions of the free and fixed layers are equal (parallel) to each other, the path passing through the free and fixed layers has a small electric resistance value. When the magnetization directions of the free and fixed layers are opposite (anti-parallel) to each other, the resistance value the path increases. An amount of a flowing current varies depending on this resistance value of the storage element. Data is read by detecting the amount of the current flowing through the storage element.
As a magnetic memory, there has been a resistance RAM (RRAM) utilizing the fact that a chalcogenide material has a resistance value varying depending on a polarity of an applied voltage pulse.
Reference 1 (Japanese Patent Laying-Open No. 2005-216387) discloses a construction aiming at writing of information in a short time. In Reference 1, a memory cell includes a resistance element and an access transistor, which are connected in series between a source line and a bit line. With an operation of changing the storage element from a high-resistance state to a low-resistance state being referred to as “writing”, the memory cell is configured to have such characteristics that a combined resistance value of the storage element and access transistor in the memory cell takes a constant value after the writing. The access transistor is formed of an MIS transistor (insulated gate type field effect transistor). When current-voltage characteristics of the MIS transistor coincide with current-voltage characteristics of the resistance element, the write operation stops. A voltage produced by resistance-division of the storage element (resistance element) and a channel resistances of and the MIS transistor is applied to the resistance element, and the writing stops when the voltage-current characteristics of the both match with each other. Thereby, the combined resistance of the access transistor and the storage element substantially takes a constant value, to suppress variations in resistances value after the writing.
Reference 2 (Japanese Patent Laying-Open No. 2004-185754) discloses a construction aiming at fast erasing/writing in an RRAM, similarly to Reference 1. In Reference 2, an erasure operation mode specifically includes two modes; a collective erasing mode for collectively erasing memory cells in an entire memory array region and an individual erasing mode for individually erasing the memory cells in the memory array region. The collective erasing mode is used for rapidly erasing data of an entire erasing target such as program data, and the individual erasing mode is used for individually erasing an individual item of data items such as code data so that an efficient erasing operation may be achieved.
In Reference 2, writing is effected on all the memory cells to be erased before the collective erasing is performed, and thus a so-called pre-erasure writing (writing before erasure) is performed so that resistance values of these memory cells are adjusted. Thereafter, all the memory cells are set to a high-resistance state, i.e., the erased state so that current consumption for applying an erasing voltage may be reduced.
According to Reference 3 (Japanese Patent Laying-Open No. 2005-092912), all memory cells in a write target region are set to a high-resistance state before a reset operation (transition to a low-resistance state) in a spin injection MRAM, for suppressing variations in resistance state after the reset operation. In a memory cell construction, a variable resistance element is connected to a source line, and is connected to a bit line via an access transistor. Thereby, it is intended to avoid occurrence of disturbance, i.e., adverse influence on storage data of unselected cell due to noises on bit line potential during writing/reading.
In the configuration of the memory cell array disclosed in Reference 3, the source lines are arranged parallel to word lines, and the bit lines are arranged being perpendicular to the source and word lines. Reference 3 discloses an approach for overcoming a problem similar to the above-described problem also in the RRAM.
In Reference 4 (Japanese Patent Laying-Open No. 2004-355670), memory cells in adjacent columns share a source line, and variable resistance elements are connected to the source line via access transistors. The bit line arranged for each column is held at a ground voltage level when it is not selected, and the bit line and source line of the memory cells in the unselected column are held at the same voltage level, to suppress application of a voltage stress to the unselected memory cells.
In this Reference 4, the reset operation is performed to set all the memory cells in an access target region to a reset state of a low resistance value, and then, the memory cells are driven to a high-resistance state in accordance with write data.
In Reference 5 (Japanese Patent Laying-Open No. 2004-185755), each source line is arranged to be shared between adjacent columns and is directly connected to a variable resistance element, which in turn is connected to a bit line via an access transistor.
This Reference 5 prevents application of a voltage, applied onto a bit line in reading/writing, on a variable resistance element, to eliminate the voltage stress on the resistance element. In addition, the current flowing path is shut off by the access transistor in an unselected memory cell to avoid the disturbance in the writing and reading. Further, by arranging the source line for each column, an erasing voltage is not applied to an unselected source line when the erasing is performed on a source line basis, to suppress the voltage stress applied to the variable resistance element in the erasing operation. Select transistors are connected in series to the opposite ends of the variable resistance element, respectively, to prevent occurrence of the disturbance in the unselected memory cell even when a voltage is applied to the source line in the erasing operation (reset operation).
In the data write operation of the MRAM, the current supplied to the memory cell flows in different directions depending on the logical value of the write data, and the current flows bidirectionally through the memory cells in the data write operation. Likewise, in the RRAM, the voltage is applied to the memory cell in different polarities depending on a logical value of the write data, and the voltage is bidirectionally applied to the memory cell. Accordingly, in either of the RRAM and MRAM, the bit line and source line must be driven bidirectionally.
According to the construction disclosed in Reference 1, the memory cell is configured to have such characteristics that the combined resistance value of the variable resistance element and the access transistor takes a constant value after the writing. It is intended to suppress variations in resistance value after the writing and to reduce variations in resistance value of the elements when these are reset. However, the construction disclosed in Reference 1 is aimed at matching the element characteristics only when the resistance state changes in one direction from the low-resistance state to the high-resistance state, and no consideration is given to the case where the data writing of selected memory cells into the low-resistance state and the high-resistance state. Particularly, Reference 1 does not consider an operation control for parallel writing of multi-bit data.
According to the construction disclosed in Reference 2, the pre-erasing writing is first performed to set the memory cells to the high-resistance state before the erasing, and then collective erasure is performed. Since the collective erasing is performed after setting the memory cells into the high-resistance state, the pre-erasing writing and the erasing are performed collectively on the memory cells regardless of the write data to the memory cells. Reference 2 does not disclose a construction for writing data to set the resistance state of the memory cells pursuant to the write data. Also, this Reference 2 does not disclose any construction for parallel writing of multi-bit data.
According to Reference 3, the access transistor is arranged between the variable resistance element and the bit line, whereby it is intended to suppress application of the bit line voltage to the variable resistance element in the write/read operations, and to suppress application of the voltage stress to an unselected cell. In Reference 3, consideration is given to overcoming the problem of the disturbance during the write/read operations, but any consideration is not given to the problem of the disturbance during the parallel writing of multi-bit data as well as the efficient writing such multi-bit data.
In the construction disclosed in Reference 4, the variable resistance element is coupled to the bit line, whereby it is intended to hold the unselected bit line at a low level and to avoid increase in both current consumption and access time. In the data write operation, an applied voltage pulse is toggled to apply the voltage pulse of a waveform of the sequence of a low voltage level, a high voltage level and a low voltage level, or of a high voltage level, a low voltage level and a high voltage level, so that the voltage pulse may be applied to the selected bit line regardless of the write operation and the reset operation. The writing operation and the reset operation are distinguished from each other according to the level of the voltage applied to the source line. In Reference 4, however, the write operation and the reset operation are executed in the different, individual operation cycles, respectively, and no consideration is given to the operation of performing the pre-erasing writing before the collective erasing, as is disclosed in References 1 and 2. Further, no consideration is given to the parallel write operation for the multi-bit data.
In the construction disclosed in Reference 5, the source line is shared by the memory cells on adjacent columns, and the variable resistance elements are connected to the source line. Thereby, it is intended to avoid the voltage stress that may be applied on the variable resistance element due to the bit line voltage. However, Reference 5 likewise gives no consideration to the construction for parallel writing of multi-bit data without increasing the layout area.